1. Technical Field
The present invention relates to a test of a semiconductor integrated circuit. More specifically, the present invention is directed to a fault list and test pattern generating apparatus, a fault list and test pattern generating method, a fault list generating and fault coverage calculating apparatus, and a fault list generating and fault coverage calculating method for a bridge fault test.
2. Description of Related Art
In accordance with the progress of shrinking of semiconductor processes, it is expected that the proportion of bridge faults among various faults occurring in semiconductor integrated circuits (LSIs) will much increase. A “bridge fault” in an LSI occurs (is assumed) in such a manner that a foreign particle (dust) is bridged over one set of signal wires (will be referred to as “signal wire pair” hereinafter) which are arranged in the adjacency to each other and can be extracted from the layout of the LSI, so that the wires are electrically shorted by the foreign particles.
Conventionally, bridge fault tests capable of detecting bridge faults have been brought into practice by use of an IDDQ (IDD Quiescent) test which can be easily applied to LSIs consisting of CMOS(Complimentary MOS) circuits which are dominant circuits of the present LSIs. In an IDDQ test, based on the fact that there is no DC current path and so that very little DC current flows in a fault-free CMOS circuit at a stable state, in such a case that a signal on one signal wire becomes “1” where a bridge fault occurs whereas a signal on the other signal wire of the corresponding signal wire pair becomes “0”, a DC current (abnormal IDDQ) value which flow through an LSI is measured so as to detect the bridge fault (the bridge fault is “activated” by these signals). Test patterns including information on IDDQ measurement times are newly generated or selected from existing test patterns for the IDDQ test for bridge faults, so that as many bridge faults can be detected by small number of IDDQ measurement times as possible. However, since the shrinking of semiconductor processes has much progressed, especially in LSIs operable in high clock frequencies, IDDQ current values of fault-free samples of such LSIs has remarkably increased and to detect abnormal IDDQ value accompanied by a bridge fault bas become vary difficult, so that the IDDQ test can be hardly applied.
As a consequence, instead of the above-explained IDDQ test, such a test capable of detecting a bridge fault in such a manner that a bridge fault detecting-purpose test pattern is inputted to an LSI, and then, a logical value of an output terminal is compared with an expected value so as to perform a good/no-good judgement (will be referred to simply as “bridge fault test” hereinafter) has become a very important test as the bridge fault test which is practically applied to LSIs (refer to, for example, patent publication 1). However, such bridge fault tests which may be applied to a recent very large-scaled LSI have not been sufficiently accomplished except for such a simple bridge fault test which merely handles a wired-AND type bridge fault or a wired-OR type bridge fault.
Generally speaking, in the case that logical values of signals of a signal wire pair where a bridge fault occurs (is assumed) are different from each other, the bridge fault is “activated”, while the activated bridge fault propagates in an LSI, and, if it is outputted to the outside of the LSI as a different logical value from that of an expected value, the bridge fault is detected. In this case, the term “propagation of bridge fault” implies such an operation that such an error signal is propagated within an LSI, while this error signal is different from a signal under fault-free condition and is produced due to an influence of a bridge fault. The error signal is propagated within the LSI and then is reached to an output terminal of the LSI, so that the bridge fault which is activated by a bridge fault test pattern and causes the generation of the error signal can be detected. In general, a test pattern used to detect a bridge fault is generated by an automatic test pattern generation (ATPG) tool which is used so as to detect a bridge fault based upon logical connection network information of an LSI. The bridge faults extracted from the layout of the LSI are processed in relation to signals appeared on the logical connection network of the LSI. It should be understood that “precision”, on a bridge fault test which, in other words, is reliability on the modeling of real bridge faults and the detection and non-detection of these faults may be largely influenced by the following various aspects, namely, driving (primitive) cells for driving two signal wires where a bridge fault occurs; logical values of input signals to the driving cells; a resistance value between electrically shorted wires; receiving (primitive) cells which receive respective signals; logical threshold values of input terminals of the receiving cells. In more details, the above-explained “precision” of the bridge fault test is given as follows;
a bridge fault behaves as which fault type; and what degree of credibility is expected at which such a bridge fault judged as “detected” or “not-detected” by a test pattern is actually detected. Therefore, it is important that these items may be extracted and modeled in high precision as being permitted as possible.
On the other hand, if the precision of detecting operation for bridge faults by the bridge fault test pattern may achieve a practical precision, even when this detecting precision is further improved, then there is such a tendency that the additional effect of the bridge fault test is lowered. Therefore, it is practically very important to generate bridge fault test patterns in a short time even for a current large-scaled LSI, with maintaining practically sufficient precision.
A bridge fault test (and test pattern) having high precision on detecting bridge faults corresponds to such a bridge fault test that an assumed bridge fault well models (describes) that which occurs in an actual LSI internal portion in higher precision; and a bridge fault judged as “detected” by an (generated) test pattern is actually (in high probability) activated and propagated within the LSI and then can be detected, also a bridge fault judged as “not-detected” by the pattern is not detected in a high probability. As previously explained, such a fact as to whether or not the bridge fault is activated and propagated in the LSI may be determined based upon the driving circuits (cells) for driving the respective signals of the signal wire pair where the bridge fault occurs; the inputs to the driving circuits; the resistance values between the signal wires of the signal wire pair, the receiving circuits (cells) into which the activated error signal on the signal wires is inputted; and the logical threshold values of the input terminals of the receiving circuits to which the error signal is inputted. However, it is very difficult to acquire all of the above-explained information in the large-scaled LSI. In general, aplenty of time is required to acquire the information, and to generate an effective bridge fault test pattern by utilizing the above-described information. As a consequence, it is practically difficult to form a bridge fault test pattern capable of detecting bridge faults in a highest precision. (See JP-A-2003-107138.)